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1
FINAL
MACH 1 & 2 FAMILIES
COM'L: -12/15
IND: -18
Lattice Semiconductor
MACH120-12/15
High-Performance EE CMOS Programmable Logic
MACH 1 & 2 Families
DISTINCTIVE CHARACTERISTICS
x 68 Pins in PLCC x 48 Macrocells x 12 ns tPD Commercial, 18 ns tPD Industrial x x x x x x x
77 MHz fCNT Commercial 48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks 48 Outputs 48 Flip-flops; 4 clock choices 4 "PALCE26V12" blocks SpeedLockingTM for guaranteed fixed timing Pin-compatible with the MACH221
GENERAL DESCRIPTION
The MACH120 is a member of the high-performance EE CMOS MACH (R) 1 family. This device has approximately five times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH120 consists of four PAL(R) blocks interconnected by a programmable switch matrix. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH120 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.
Publication# 14129 Amendment/0
Rev: J Issue Date: November 1997
BLOCK DIAGRAM
Block A
I/O0-I/O11 12 I/O Cells 12 Macrocells OE 52 x 54 AND Logic Array and Logic Allocator 26 Switch Matrix OE 52 x 54 AND Logic Array and Logic Allocator 26 Macrocells 4 I/O Cells 12 4 Block B I/O12-I/O23 12 I2-I3 I6-I7
MACH 1 & 2 Families
26 52 x 54 AND Logic Array and Logic Allocator OE Macrocells 12 I/O Cells 12
26 52 x 54 AND Logic Array and Logic Allocator OE Macrocells 12 I/O Cells 12 4
4
I/O36-I/O47 Block D
I/O24-I/O35 Block C CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5
14129J-1
MACH120-12/15
3
CONNECTION DIAGRAM
Top View
PLCC
Block A
Block D
I/O7 I/O8 I/O9 I/O10 I/O11 CLK0/I0 CLK1/I1 I2 VCC GND I3 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17
10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O6 GND I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 GND
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I7 GND VCC I6 CLK3/I5 CLK2/I4 I/O35 I/O34 I/O33 I/O32 I/O31
GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30
Block B
Note: Pin-compatible with the MACH220 and MACH221.
Block C
14129J-2
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I I/O VCC = Input = Input/Output = Supply Voltage
4
MACH120-12/15
ORDERING INFORMATION
Commercial Products
Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 120 -12 J C
MACH 1 & 2 Families
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPERATING CONDITIONS C = Commercial (0C to +70C) PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068)
DEVICE NUMBER 120 = 48 Macrocells, 68 Pins SPEED -12 = 12 ns tPD -15 = 15 ns tPD
Valid Combinations MACH120-12 JC MACH120-15
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid combinations and to check on newly released combinations.
MACH120-12/15 (Com'l)
5
ORDERING INFORMATION
Industrial Products
Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 120 -18 J I
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPERATING CONDITIONS I = Industrial (-40C to +85C) PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068)
DEVICE NUMBER 120 = 48 Macrocells, 68 Pins SPEED -18 = 18 ns tPD
Valid Combinations Valid Combinations MACH120-18 JI The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid combinations and to check on newly released combinations.
6
MACH120-18 (Ind)
FUNCTIONAL DESCRIPTION
The MACH120 consists of four PAL blocks connected by a switch matrix. There are 48 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are 4 clock pins that can also be used as dedicated inputs. The PAL Blocks Each PAL block in the MACH120 (Figure 1) contains a 48-product-term logic array, a logic allocator, 12 macrocells and 12 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an independent "PALCE26V12". There are four additional output enable product terms in each PAL block. For purposes of output enable, the 12 I/O cells are divided into 2 banks of 6 macrocells. Each bank is allocated two of the output enable product terms. An asynchronous reset product term and an asynchronous preset product term are provided for flip-flop initialization. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACH120 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 12 internal feedback signals and 12 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-Term Array The MACH120 product-term array consists of 48 product terms for logic use, and 6 special-purpose product terms. Four of the special-purpose product terms provide programmable output enable, one provides asynchronous reset, and one provides asynchronous preset. Two of the output enable product terms are used for the first six I/O cells; the other two control the last six macrocells. The Logic Allocator The logic allocator in the MACH120 takes the 48 logic product terms and allocates them to the 12 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers.
Table 1.
Output Macrocell M0 M1 M2 M3 M4 M5 Available Clusters C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6
MACH 1 & 2 Families
Logic Allocation
Output Macrocell M6 M7 M8 M9 M10 M11 Available Clusters C5, C6, C7 C6, C7, C8 C7, C8, C9 C8, C9, C10 C9, C10, C11 C10, C11
MACH120-12/15
7
The Macrocell The MACH120 macrocells can be configured as either registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured as registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of four global clock pins, which are also available as logic inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The I/O Cell The I/O cell in the MACH120 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to six I/O cells. Within each PAL block, two product terms are available for selection by the first six three-state outputs; two other product terms are available for selection by the last six three-state outputs. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 architecture is designed for high performance--a metric that is met in both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the central switch matrix, the MACH 120 product offers the SpeedLocking feature, which allows a stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to 16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs
8
MACH120-12/15
MACH 1 & 2 Families
0
4
8
12
16
20
24
28
32
36
40
43
47
51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset
M0
Output Macro Cell
I/O Cell
I/O
M1
Output Macro Cell
I/O Cell
I/O
I/O Cell
0
M2 C0 C1 C2 C3 C4 Logic Allocator M4 M3
Output Macro Cell
I/O
Output Macro Cell
I/O Cell
I/O
I/O Cell Output Macro Cell
I/O
Switch Matrix
C5 C6 C7 C8 C9
I/O Cell
I/O
M5
Output Macro Cell
M6
Output Macro Cell
I/O Cell
I/O
C10
47
M7
Output Macro Cell
I/O Cell
I/O
C11 M8
Output Macro Cell
I/O Cell
I/O
M9
Output Macro Cell
I/O Cell
I/O
M10
Output Macro Cell
I/O Cell
I/O
I/O Cell
I/O
M11
Output Macro Cell
Output Enable Output Enable 0 4 8 12 16 20 24 28 32 36 40 43 47 51 CLK 4 12 12
14129J-3
Figure 1.
MACH120 PAL Block
MACH120-12/15
9
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . -65C to +150C Ambient Temperature With Power Applied . . . . . . . . . . . . . .-55C to +125C Device Junction Temperature . . . . . . . . . . . . . +150C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 70C) . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 16 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = 5 V, TA=25C, f = 25 MHz (Note 4) -30 85 2.0 0.8 10 -10 10 -10 -130 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset.
10
MACH120-12/15 (Com'l)
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Conditions VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
MACH 1 & 2 Families
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH External Feedback fMAX Maximum Frequency (Note 1) -12 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Clock Hold Time Clock to Output LOW CLock Width HIGH D-type T-type 6 66.7 62.5 76.9 71.4 83.3 16 12 8 16 12 8 12 12 15 10 15 15 15 10 20 6 50 47.6 66.6 55.5 83.3 20 ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns 6 D-type T-type 7 8 0 8 6 Min Max 12 10 11 0 10 Min -15 Max 15 Unit ns ns ns ns ns ns
D-type Internal Feedback (fCNT) T-type No Feedback
tAR tARW tARR tAP tAPW tAPR tEA tER
Asynchronous Reset to Registered Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected.
2. See Switching Test Circuit, for test conditions.
MACH120-12/15 (Com'l)
11
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . -65C to +150C Ambient Temperature With Power Applied . . . . . . . . . . . . . -55C to +125C Device Junction Temperature . . . . . . . . . . . . . +150C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
INDUSTRIAL OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 16 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -30 85 2.0 0.8 10 -10 10 -10 -130 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) Supply Current (Typical) VCC = 5 V, TA = 25C, f = 25 MHz (Note 4)
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.
12
MACH120-18 (Ind)
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Conditions VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
MACH 1 & 2 Families
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH -18 Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) D-type Setup Time from Input, I/O, or Feedback T-type Hold Time Clock to Output (Note 3) Clock Width External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) LOW HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tAR tARW tARR tAP tAPW tAPR tEA tER Asynchronous Reset to Registered Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3) 18 12 18 18 18 12 24 T-type 1/(tWL + tWH) 7.5 7.5 40 38 53 44 66.5 24 13.5 0 12 ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns 12 Min Max 18 Unit ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 24 outputs switching.
MACH120-18 (Ind)
13
TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25C
IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 -40 -60 -80 Output, LOW
14129
.2
.4
.6
.8
1.0
IOH (mA) 25 -3 -2 -1 -25 -50 -75 -100 -125 -150 Output, HIGH
14129J-5
1
2
3
4
5 VOH (V)
II (mA) 20 VI (V) -2 -1 -20 -40 -60 -80 -100 Input
14129J-6
1
2
3
4
5
14
MACH120-12/15
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25C
MACH 1 & 2 Families
150 ICC (mA) 125
100
75
50 25
0 0 10 20 30 40 50 Frequency (MHz) 60 70
14129J-7
The selected "typical" pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
MACH120-12/15
15
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient 200 lfpm air jma Thermal impedance, junction to ambient with air flow 400 lfpm air 600 lfpm air 800 lfpm air Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are taken with components on a six-layer printed circuit board. PLCC 13 37 33 30 28 25 Unit C/W C/W C/W C/W C/W C/W
SWITCHING WAVEFORMS
Input, I/O, or Feedback VT tPD Combinatorial Output Combinatorial Output Input, I/O, or Feedback tS Clock VT tCO Registered Output Registered Output tWH Clock tWL
14129J-10
VT
14129J-8
VT tH
VT
14129J-9
Clock Width
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
16
MACH120-12/15
SWITCHING WAVEFORMS
tARW Input, I/O, or Feedback tAR Registered Output VT VT
MACH 1 & 2 Families
tARR Clock VT
14129J-11
Asynchronous Reset tAPW Input, I/O, or Feedback tAP Registered Output VT tAPR Clock VT VT
14129J-12
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5 V VOL + 0.5 V
VT tEA VT
14129J-13
Output Disable/Enable
Notes: 1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH120-12/15
17
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 CL Test Point
14129J-14
Commercial Specification tPD, tCO tEA tER Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 5 pF 35 pF 300 390 H Z: VOH - 0.5 V L Z: VOL + 0.5 V 1.5 V S1 CL R1 R2 Measured Output Value
*Switching several outputs simultaneously should be avoided for accurate measurement.
18
MACH120-12/15
FMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
(SECOND CHIP)
MACH 1 & 2 Families
CLK
LOGIC
REGISTER
LOGIC
REGISTER
tS
tCO
tS
fMAX Internal (fCNT) CLK
fMAX External 1/(ts + tCO) CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL)
tHIR tSIR fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
MACH120-12/15
19
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using Vantis' advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics
Parameter Symbol tDR N Parameter Description Min Pattern Data Retention Time Max Reprogramming Cycles 10 20 100 Units Years Years Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 k 1 k VCC
ESD Protection Input VCC VCC
100 k 1 k
Preload Circuitry
Feedback Input I/O 14129J-15
20
MACH120-12/15
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are:
1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Symbol tPR tS tWL Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
MACH 1 & 2 Families
Parameter Descriptions
Max 10
Unit s
See Switching Characteristics
VCC Power 4V tPR Registered Output tS Clock
tWL
14129J-16
Power-Up Reset Waveform
MACH120-12/15
21

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